peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2003 page 1 of 7 exposed solder pad (bottom side) v dd gnd rf1 rf2 gnd ctrl 4 5 6 3 2 1 product description figure 1. functional schematic diagram rf1 rf2 ctrl 75 ? figure 2. pin configuration table 1. electrical specifications @ +25 c (z s = z l = 75 ? ) parameter condition minimum typical maximum units operating frequency 1 dc 1300 mhz insertion loss dc ? 50 mhz 1000 mhz 0.5 0.8 0.65 1.0 db isolation dc ? 50 mhz 1000 mhz 80 58 85 60 db return loss dc - 1000 mhz 16 20 db input 1 db compression 2,4 1000 mhz 30 33 dbm input ip2 2 1000 mhz 80 dbm input ip3 2 1000 mhz 50 dbm video feedthrough 3 15 mv pp switching time 2 s notes: 1. device linearity will begin to degrade below 1 mhz. 2. measured in a 50 ? system. 3. measured with a 1 ns risetime, 0/3 v pulse and 500 mhz bandwidth. 4. note absolute maximum ratings in table 3. product specification pe4249 spst catv mosfet switch features ? 75-ohm impedance switch ? non-reflective at rf1, open reflective at rf2 when off ? 75-ohm (0.25 watt) termination ? high isolation: 85 db at 5 mhz, 60 db at 1 ghz ? low insertion loss: 0.5 db at 5 mhz, 0.8 db at 1 ghz ? high input ip2: >80 dbm ? cmos/ttl single-pin control ? single +3 volt supply operation ? extremely low bias: 33 a @ 3v the pe4249 is a high-isolation mosfet switch designed for catv applications, covering a broad frequency range from dc up to 1.3 ghz. this single- supply spst switch integrates a single-pin cmos control interface, and is non-reflective at port rf1 and open reflective at port rf2 when commanded off. it also provides low insertion loss with extremely low bias requirements while operating on a single 3-volt supply. in a typical catv application, the high isolation pe4249 can replace bulky and expensive mechanical switches. the pe4249 is manufactured in peregrine?s patented ultra thin silicon (utsi ? ) cmos process, offering the performance of gaas with the economy and integration of conventional cmos.
pe4249 product specification copyright ? peregrine semiconductor corp. 2003 file no. 70/0110~00c | utsi ? cmos rfic solutions page 2 of 7 table 2. pin descriptions pin no. pin name description 1 v dd nominal 3 v supply connection. 1 2 gnd ground connection. 3 3 rf1 rf port . 2 4 ctrl cmos or ttl logic level: high = rf1 to rf2 signal path low = rf1 isolated from rf2 5 gnd ground connection . 3 6 rf2 rf port . 2 notes: 1. a bypass capacitor should be placed as clos e as possible to the pin. 2. both rf pins must be dc bl ocked by an external capacitor or held at 0 v dc . 3. the exposed pad must be soldered to the ground plane for proper switch performance. table 3. absolute maximum ratings symbol parameter/condition min max unit v dd power supply voltage -0.3 4.0 v v i voltage on ctrl input -0.3 5.5 v t st storage temperature -65 150 c t op operating temperature -40 85 c p in input power (50 ? ), ctrl=1/ctrl=0 33/24 dbm v esd esd voltage (human body model) 500 v table 4. dc electrical specifications @ 25 c parameter min typ max unit v dd power supply 2.7 3.0 3.3 v i dd power supply current (v dd = 3v, v cntl = 3v) 33 40 a control voltage high 70% v dd 5 v control voltage low 0 30% v dd v electrostatic discharge (esd) precautions when handling this utsi device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, utsi cmos devices are immune to latch-up. device description the pe4249 high isolation spst catv switch is designed to support catv applications such as premium channel service connect/disconnect switch blocks. this function is typically performed by bulky and expensive mechanical switches. the high isolation characteristics (60 db at 1 ghz, 85 db at 5 mhz), high compression point, and an integrated 75 ? (0.25 watt) input termination make the pe4249 an ideal, low cost solution. figure 3. typical application block diagram 2-way splitter premium channel filter pe4249 pe4249 catvin catvout table 5. truth table control voltage (ctrl) signal path (rf1 to rf2) high 1 on low off notes: 1. ctrl accepts both cmos and ttl voltage leads. the control logic input pin (c trl) is typically driven by a 3-volt cmos logic level signal, and has a threshold of 50% of v dd . for flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5- volt logic high signal. (a minimal current will be sourced out of the v dd pin when the control logic input voltage level exceeds v dd. )
pe4249 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2003 page 3 of 7 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0 200 400 600 800 1000 1200 insertion loss (db) frequency (mhz) -40 ! c 25 ! c 85 ! c -100 -80 -60 -40 -20 0 0 200 400 600 800 1000 1200 isolation (db) frequency (mhz) 20 30 40 50 60 20 30 40 50 60 0 200 400 600 800 1000 1200 iip3 (dbm) 1db compression point (dbm) frequency (mhz) iip3 input 1db compression typical performance data @ -40 c to 85 c (unless otherwise noted) (75-ohm impedance except as indicated) figure 4. insertion loss figure 5. input 1 db compression point & iip3 (50-ohm system impedance) figure 6. isolation
pe4249 product specification copyright ? peregrine semiconductor corp. 2003 file no. 70/0110~00c | utsi ? cmos rfic solutions page 4 of 7 -30 -24 -18 -12 -6 0 0 200 400 600 800 1000 1200 return loss (db) frequency (mhz) -40 ! c 25 ! c 85 ! c -30 -25 -20 -15 -10 -5 0 0 200 400 600 800 1000 1200 return loss (db) frequency (mhz) -40 ! c 25 ! c 85 ! c -40 -35 -30 -25 -20 -15 -10 -5 0 0 200 400 600 800 1000 1200 return loss (db) frequency (mhz) -40 ! c 25 ! c 85 ! c typical performance data @ -40 c to 85 c (unless otherwise noted) (75-ohm impedance) figure 7. rf1 return loss (switch = on) figure 8. rf2 return loss (switch = off) figure 9. rf1 return loss (switch = off)
pe4249 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2003 page 5 of 7 evaluation kit information evaluation kit the spst switch evaluation kit board was designed to ease customer evaluation of the pe4249 spst switch. the rf1 port is connected through a 75 ? transmission line to the top left bnc connector, j1. the rf2 port is connected through a 75 ? transmission line to the bnc connector on the top right side of the board, j2. a through transmission line connects bnc connectors j3 and j4. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a two metal layer fr4 material with a total thickness of 0.031?. the bottom layer provides ground for the rf transmission lines. the transmission lines were designed using a coplanar waveguide model with trace width of 0.021?, trace gaps of 0.030?, dielectric thickness of 0.028?, metal thickness of 0.0021? and r of 4.3. note that the predominate mode for these transmission lines is coplanar waveguide with a ground plane. j5 provides a means for controlling dc and digital inputs to the device. starting from the lower left pin, the second pin to the right (j5-3) is connected to the device v dd input. the fourth pin to the right (j5-7) is connected to the device ctrl input. a decoupling capacitor (100 pf) is provided on both traces. it is the responsibility of the customer to determine proper supply decoupling for their design application. removing these components from the evaluation board has not been shown to degrade rf performance. figure 10. evaluation board layouts figure 11. evaluation board schematic vdd ctrl rf1 gnd gnd rf2 100 pf optional j1 j2 j3 j4 j5-7 100 pf optional j5-3
pe4249 product specification copyright ? peregrine semiconductor corp. 2003 file no. 70/0110~00c | utsi ? cmos rfic solutions page 6 of 7 edge of plastic body this feature applies to both ends of the pkg. detail a exposed slug/ heat sink exposed metalized feature 0.17 min. 0.24 +0.20 -0.08 0.125 0.17 0.30 0.025 0.025 detail b (2x) exposed 6 5 3 bottom view 2 1 4 3 0.10 c a b 0.05 c 0.95 l c 0.35 +0.08 -0.02 0.29 +0.21 -0.08 1.21 0.10 0.605 0.05 1.050.05 2.010.10 exposed pad see detail a r0.127 typ .20 min. r 0.15 typ seating plane side view top view - c - 0.100 c 0.080 c 0.70 0.05 0.20 0.05 0.90 0.10 0.0250.025 10 +2 -10 detail c see detail b 3 1 pin 1 mark c l c l 3.00 0.125 3.00 0.125 0.10 c 0.10 c 23 6 54 4 4 - a - - b - 3 coplanarity applies to exposed heat slug as well as the terminals. 4 profile tolerance applies to plastic body only. 1. dimensions and tolerances are per ansi y14.5 2. dimensions are in millimeters, angles are in degrees. figure 12. package drawing 6-lead mlpm table 6. ordering information order code part marking description package shipping method 4249-01 4249 pe4249-06mlp3x3-12800f 6-lead 3x3mm mlpm 12800 units / canister 4249-02 4249 pe4249-06mlp3x3-3000c 6-lead 3x3mm mlpm 3000 units / t&r 4249-00 pe4249-ek pe4249-06mlp3x3-ek evaluation board 1 / box
pe4249 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2003 page 7 of 7 sales offices united states peregrine semiconductor corp. 6175 nancy ridge drive san diego, ca 92121 tel 1-858-455-0660 fax 1-858-455-0770 japan peregrine semiconductor k.k. 5a-5, 5f imperial tower 1-1-1 uchisaiwaicho, chiyoda-ku tokyo 100-0011 japan tel: 03-3507-5755 fax: 03-3507-5601 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f- 92380 garches tel 33-1-47-41-91-73 fax 33-1-47-41-91-73 australia peregrine semiconductor australia 8 herb elliot ave. homebush, nsw 2140 australia tel: 011-61-2-9763-4111 fax: 011-61-2-9746-1501 for a list of representatives in your area, please refer to our web site at: http://www.peregrine-semi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target s pecifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final dat a. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a pcn (product change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. peregrine products are protected under one or more of the following u.s. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. other patents are pending. peregrine, the peregrine logotype, peregrine semiconductor corp., and utsi are registered trademarks of peregrine semiconductor corporation. copyright ? 2003 peregrine semic onductor corp. all rights reserved.
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